1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to testing and emulation of integrated circuits.
2. Description of Related Art
Advances in integrated circuit technology allow combining the components which were manufactured as separate integrated circuits into one integrated circuit. For example, a microprocessor, a gate array and a peripheral device typically manufactured as three separate (discrete) integrated circuits can now be embedded into one integrated circuit. Combining such components into one integrated circuit reduces the manufacturing costs and the size of the circuitry. The reliability is also improved as the problems associated with interconnecting discrete components on a printed circuit board are eliminated.
The testing of each component, however, is more complicated when the components are embedded into one integrated circuit because some internal connections of the components are not accessible from the external pins. The test vectors written for each individual component become unusable. Writing a new set of test vectors to test the circuit with the embedded components is expensive and time consuming.
Various techniques have been developed to access the internal connections of the components without adding a large number of external pins. In the "scan path" technique, the flip-flops of the integrated circuit are replaced by specially designed flip-flops each of which has a normal data input and a test data input. The flip-flops are interconnected into a shift register. The data can be shifted into each flip-flop through the test data inputs and shifted out through the flip-flop normal output. During testing, all the data are shifted in from one external pin into the flip-flops, the integrated circuit is clocked, and then the data are shifted out. The shifted-out data are analyzed so as to analyze the performance of the integrated circuit. This method, however, does not allow access to every internal connection of the embedded components.
In a "muxed I/O" technique illustrated in FIG. 1, every I/O node of every component is multiplexed, for testing purposes, to an external pin. The integrated circuit 110 of FIG. 1 has N function block 120.1 through 120.N each of which is an embedded component. The output node 130.1 of function block 120.1 is internally connected by line 140.1 to function block 120.N and, perhaps, to other function blocks. The line 140.1 is also connected to an N+1:1 multiplexer 150 which forms part of an I/O buffer 160.1 connected to the external pin 170.1. Multiplexer 150 multiplexes N test-mode connections from nodes 130.1, . . . , 130.N and a normal-mode connection 174 to pin 170.1. In normal mode, multiplexer 150 selects line 174. During testing, for example, of function block 120.1, multiplexer 150 selects the line 140.1.
Similarly, each input node 178.i of function block 120.i has an associated multiplexer 182.i. In normal mode, each multiplexer 182.i selects its normal-mode input IN connected to other function blocks in normal mode. In test mode, multiplexer 182.i selects its test input TIN connected to an external pin such as pin 170.2. The I/O buffer 160.2 of pin 170.2 contains a demultiplexer 186 which in test mode selects the line 188 connected to the inputs TIN of multiplexers 182.i. In normal mode, demultiplexer 186 selects the normal mode output 192.
In the integrated circuit 110 of FIG. 1, every I/O node of every function block 120.i is accessible from an external pin. However, the architecture of FIG. 1 reduces the speed of the circuit because the connections from the output nodes 130.i to the multiplexers such as multiplexer 150 present additional loading on the output nodes. Further, a large number of external pins are required to accommodate testing. In particular, one pin such as pin 170.1 is required for each output node of a given function block, though the same pin can be used for different output nodes of different function blocks. Similarly, one pin such as pin 170.2 is required for each input of a given function block. Thus the total number of the external pins required for testing is the maximum number of the output nodes in any one function block plus the maximum number of the input nodes. For example, if function block 120.1 has 40 output nodes and 10 input nodes and function block 120.N has 40 input nodes and 10 output nodes, the total number of pins required is eighty: 40 output pins and 40 input pins. It is desirable to reduce the number of the external pins required for testing and to reduce the loading of the test circuitry on the normal mode operation.
Embedding the components into one integrated circuit also complicates the emulation of the embedded devices such as microprocessors and microcontrollers. For example, FIG. 2 shows an integrated circuit 210 which includes microcontroller 120.1 and another function block 120.2. If blocks 120.1, 120.2 were discrete components, an in-circuit emulator (ICE) generally available for microcontroller 120.1 could be connected to function block 120.2 to replace the microcontroller. However, in integrated circuit 210, the internally connected nodes 220, 230 of function block 120.2 are not accessible to the emulator.
One approach to the problem is to create a separate emulator for the integrated circuit 210. Creating a separate emulator, however, is quite expensive.
Another approach is to emulate the integrated circuit 210 by discrete components so as to connect a stand-alone emulator of microcontroller 120.1 to a discrete component corresponding to function block 120.2. This approach, however, does not emulate the integrated circuit with sufficient precision because the timing and the layout in the discrete components is typically different from that in the combined integrated circuit.
A third approach is to create a "bond-out" device shown in FIG. 3. In the integrated circuit of FIG. 3, every internal connection is broken and brought out to an additional external pin. The internal nodes 220, 230 of function block 120.2 become accessible to the emulator. Further, every function block is accessible for testing. However, the layout of the bond-out device is typically different from the layout of the integrated circuit 210 of FIG. 2. Hence the emulation precision is sacrificed.
Thus there is a need for an emulation technique which provides high precision emulation and which permits using an ICE for a stand-alone microcontroller so as not to require an ICE for an entire integrated circuit.